The present invention relates to a semiconductor integrated circuit including internal circuits and electrostatic discharge protection circuits, and in particular, relates to a technique effective at reducing an increase in the number of electrostatic discharge protection circuits or the number of electrostatic discharge protection elements due to increases in the number of separations of power voltages and the number of separations of ground voltages.
Heretofore, semiconductor integrated circuits have included ESD protection circuits to protect the semiconductor integrated circuits from damage caused by electrostatic discharge (ESD).
In such a semiconductor integrated circuit, a power voltage supplied to an internal circuit is lowered by transistor miniaturization for higher speed, whereas a relatively high power voltage is supplied to an input/output circuit (I/O circuit) for inputting and outputting input/output signals of a relatively high voltage level with the outside of the semiconductor integrated circuit. Further, a relatively low power voltage is supplied to an internal circuit such as a digital logic circuit configured with miniaturized transistors, whereas a relatively high power voltage is supplied to an analog circuit such as an analog/digital converter and a digital/analog converter.
Thus, in the semiconductor integrated circuit, a plurality of internal circuits that have not only different power voltages but also different circuit operations are integrated. Further, in large-scale semiconductor integrated circuits, power terminals and ground terminals are separated to prevent noise coupling, power fluctuation, and ground fluctuation.
The following non-patent documents 1 and 2 describe a whole-chip ESD protection scheme for preventing ESD damage to internal circuits in a CMOS-IC having three kinds of power voltages of 2.5, 3, and 5 V. In this scheme, a 2.5-V internal circuit, a 3-V internal circuit, and a 5-V internal circuit are coupled through bi-directional ESD coupling cells to a second ESD bus to which a ground voltage is supplied, the 2.5-V internal circuit is coupled through a bi-directional ESD coupling cell to a first ESD bus to which a power voltage of 2.5 V is supplied, the 3-V internal circuit is coupled through a bi-directional ESD coupling cell to a fourth ESD bus to which a power voltage of 3 V is supplied, and the 5-V internal circuit is coupled through a bi-directional ESD coupling cell to a third ESD bus to which a power voltage of 5 V is supplied. Further, an ESD clamp cell is coupled between the first ESD bus to which the power voltage of 2.5 V is supplied and the second ESD bus to which the ground voltage is supplied, an ESD clamp cell is coupled between the first ESD bus to which the power voltage of 2.5 V is supplied and the fourth ESD bus to which the power voltage of 3 V is supplied, an ESD clamp cell is coupled between the fourth ESD bus to which the power voltage of 3 V is supplied and the second ESD bus to which the ground voltage is supplied, an ESD clamp cell is coupled between the fourth ESD bus to which the power voltage of 3 V is supplied and the third ESD bus to which the power voltage of 5 V is supplied, and an ESD clamp cell is coupled between the third ESD bus to which the power voltage of 5 V is supplied and the second ESD bus to which the ground voltage is supplied.
[Non-Patent Document 1]    Ming-Dou Ker et al, “Whole-Chip ESD Protection Strategy for CMOS IC's with Multiple Mixed-Voltage Power Pins”, 1999 International Symposium on VLSI Technology, Systems, and Applications, PP. 298-301.
[Non-Patent Document 2]    Ming-Dou Ker et al, “ESD BUSES FOR WHOLE-CHIP ESD PROTECTION”, Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, Volume 1, PP. 545-548.